Yeah, this was a big dilemman You can't compare two different compilers for two different hw targets. That would be like benchmarking GCC compiling to ARM with LLVM compiling to x86.
Thierry's synthesis scripts are really very clever, and the go way beyond our Platypus FPGA arch. We are realistic that until we have seilicon nobody cares about our arch. Releasing the work as open source, we think someone should adapt the code for all of the other targes I Yosys (xilinx, lattice...etc) so that everyone can benefit.
We contribute a lot of code to open source, but as an FPGA vendor we are not going to spend time/money optimizing compilers for our competitors:-)
They’re showcasing their open-source stack, built on existing tools, for their own FPGA.
Imagine if, 25 years ago, a company had designed a new CPU ISA and core and, as part of the development process, ported GCC and done a nice job
tuning the existing optimization passes, with the intention of the GCC port being the primary toolchain that commercial users would use. They could write a blog post about it, and it would have been great. Maybe they even would have acknowledged in the blog post that the stack included binutils :)
in that case, such a company would be wise to include the fact that the "z1060" is a new CPU instead of failing to even mention what it is in their "new GCC port" press release page
I am sorry you that's how it looks...can't argue with feelings, We did everything we could to give credit. Open source SW should be a stack and every project needs a proper name as a reference. I do find the statement a bit ironic though, b/c 99% of Yosys users don't know that 99% of the logic synthesis sauce in Yosys is done by ABC.
I think most people who seriously use Yosys already know that ABC is the foundation it’s built on. But let’s be real, this plugin is just twelve C++ source files. Calling that a “synthesis suite” just isn’t accurate. What it actually does is build on the synthesis suite provided by Yosys (and indirectly ABC), adding some extra algorithms and support for your FPGA family.
That said, this work is important, you do need it to get your FPGA running. And from the table, the reported optimizations look good (though I haven’t dug into them in detail). Still, describing it as “a synthesis suite” when it’s really “a plugin that adds FPGA support and a few optimizations to Yosys” does indeed leave me with a bad taste in my mouth.
Of course, you don’t have to agree with me. It’s clear from other comments that not everyone does, and that’s totally fine.
There's an option for the US to buy an additional 5% if Intel sells so it doesn't have majority ownership of its fabs.
But I think the real strings are a soft, private insistence that Intel won't be allowed to sell itself overseas.
The Defense Production Act and the Committee on Foreign Investment in the United States would be used to prevent the sale. The carrot is the whatever $18B in grants and investment, the stick is legislation that allows the government to prevent a sale.
No strings common share purchase means cash in hand, which implies Intel can spend it on any operational cost, including buying billions in TSMC wafers (which they already do).
Weird title, makes it seem like a reveleation. There have been numerous Viking treasures discovered in Sweden with traces from the the Islamic world and it's well known that they were all over England as well.
The only novelty claimed here is transparency. Binary compatibility is possible by documenting the complete architecture and the sequence of bit stream loading. It only refers to devices in the same architecture (eg z1000).
We'll see whether binary compatibility is a big deal to folks. Some would argue that you can always recompile the source code. There are applications where that is not an option...
First off, this is an eFPGA core not a chip. It's intended for folks who want to build their own ASICs with a small amount of embedded FPGA logic.
The LUT is a boring text book 4-LUT. Fancier versions are in the works. The point of the first standard is to be the lowest common denominator of FPGAs that anyone can implement, else the threshold is too high. Kind of like RV32I.
Oh no, we have lost another giant! Very few people in the world know the gratitude she is owed. I doubt Nvidia and the other fabless companies would exist without her contribution. I met her through DARPA in 2018 [ref] and I later reached out for advice when I started a company in 2020. She was kind and generous with her time in all of our interactions. Beyond her technical prowess, she really understood people. The community/collabroation aprpach she used to launch the VLSI revolution in the 1970's are worth studying.
Thierry's synthesis scripts are really very clever, and the go way beyond our Platypus FPGA arch. We are realistic that until we have seilicon nobody cares about our arch. Releasing the work as open source, we think someone should adapt the code for all of the other targes I Yosys (xilinx, lattice...etc) so that everyone can benefit.
We contribute a lot of code to open source, but as an FPGA vendor we are not going to spend time/money optimizing compilers for our competitors:-)