I didn’t like that you are not supporting Linux in your free tier.
Edit: if it is not clear, the way you treat the community is one way I evaluate my decisions to support or not your company when I suggest using your products to others, students or not.
a.k.a. Just use a microcontroller. And for the vast majority of hobby projects I suspect that is good advice. Low end FPGAs don't compete well with low end microcontrollers and more people know how to use microcontrollers.
I think the reality is the niche that FPGAs occupied is getting hit hard on the high and low end. Cheap Chinese FPGAs are prevalent, cheap microcontrollers more so, and on the high-end making an ASIC that compete with a high-end FPGA has never been cheaper, and is getting cheaper and easier everyday. 65-28nm is very easy to use now (relatively speaking) and is very low cost with tons of tape outs and there is good competition. Beating an FPGA with an ASIC is not all that hard. Grad students at CMU, Stanford, Georgia Tech, etc. do it all the time in their tape-out class. Making an ASIC is not as easy as an FPGA for sure, especially if you need DDR and serdes. And NRE for ASICs for small volume ( <1K units) is higher. But it is getting easier and cheaper everyday. And it's now feasible for small teams (say ~6) to do it. I think they need to look very hard at where they spend their NRE now to stay relevant and they need to start getting brutal because I am sure the amount of revenue they're bringing in is under serious attack.
As to why Windows and not Linux? It's probably cheaper for them to maintain Windows for one reason or another. Maybe they don't even do it an just contract it out and Windows contractors are easier to find, but I'll bet it's just a basic cost issue at the end of the day.
Are you seriously suggesting hobbyists should tapeout an ASIC instead of use an FPGA?
1. For one-off designs (quantity=1) ASICs will never beat a high end FPGA on unit price.
2. As a hobbyist, you want to EXPERIMENT. You cannot do that with an ASIC. Hobbyists want to do something simple, test it on real hardware, and slowly build up from that. I don't have the time nor expertise nor motivation to spend months writing verification to get it right the first time for a tapeout.
"Just use a microcontroller"... I will concede that microcontrollers do cover 90% of hobbyists use cases (that number increasing by the day). But for hobbyists sometimes you want to learn HDL or digital logic or computer engineering. You can do this hands on with a FPGA much more effectively than in software.
> It's probably cheaper for them to maintain Windows for one reason or another.
They already need to maintain the Linux build for all the other paid tiers?? These are the same software with different features locked behind a license key. It costs them NOTHING to keep the build enabled for free tier.
> Are you seriously suggesting hobbyists should tapeout an ASIC instead of use an FPGA?
No. I said the low-end of FPGA sales is getting eaten by microcontrollers and the high-end of FPGAs sales is probably about to get eaten by custom ASICs.
Although the cost of making an ASIC is high, in the larger nodes it's not that high, and getting ever cheaper at FPGA performance levels and logic densities. FPGAs are terribly inefficient with their HW they're very easy to beat with an ASIC. They only get away with it because the NRE today is lower. But it's not an order of magnitude lower and I'm not sure how much longer that will be the case in nodes at 28nm and larger based on what I know Universities pay in tape-out classes.
Will there be very low qty projects where the NRE of developing an ASIC overwhelms that of an ASIC, sure. But will there be enough business in that niche to sustain the business of AMD, Intel and Lattice? Not obvious.
And I don't think the FPGA hobbyist market of people who "want to learn HDL" spends enough money to affect what's coming and this decision from AMD reflects that.
> 1. For one-off designs (quantity=1) ASICs will never beat a high end FPGA on unit price.
Never say never. These guys were able to convince investors you're wrong about that. :)
> No. I said the low-end of FPGA sales is getting eaten by microcontrollers and the high-end of FPGAs sales is probably about to get eaten by custom ASICs.
You have absolutely no idea what an ASIC costs compared to a FPGA. A FPGA that can compete with a tinytapeout chip costs a few dollars at most in extremely low quantites. Something high performance would need probably TSMC 12nm or similar at a minimum. At that point, you're talking $1M+ between licensing fees and direct costs to just go on a shuttle. If you want to make your own higher volume run or can't wait for shuttle spot, you're looking easily $5-10M minimum for your first 6 wafers. Comparatively, FPGAs competitive with TSMC 12nm run from a few hundred dollars up to several thousand dollars each. So for low volume, they're very competitive.
Are you sure you actually know what you're talking about?
FPGA unit costs keep doing down and they usually tend to use a recent manufacturing process. Meanwhile the fixed NRE costs of ASICs keep going up the more advanced the manufacturing process is.
An FPGA consists of non programmable logic components such as DSPs, block RAM, NoCs, SERDES/configurable IO, that keep scaling with the manufacturing process.
If you try to replicate this with an older process to cut costs, you will have an area and energy efficiency penalty.
This means that FPGAs have become more relevant over time.
> Just use a microcontroller. And for the vast majority of hobby projects I suspect that is good advice.
I recently bought a hobby FPGA kit because I think the Von Neumann model is a beautiful innovation and I want to learn more about doing useful computation tasks from the lowest level logical components. I've always been interested in computers, but when I was in grade school the only useful computers I could afford were discarded PCs that I brought back to life with Linux distros. I now have a fulfilling career as a direct result of access to cheap hardware and open-source software when I had much more time and much less money than I do now. Decisions like AMD's are a long-term negative for the industry.
As for hobbyists, in the world of $0.03 microcontrollers, strong competition on the low end from Chinese manufacturers, and where few people learn HDLs, is NRE money in the hobby market really money well spent?
I'm a HW designer and even I use microcontrollers now for most things, but not everything, because it's usually cheaper and faster.
With semiconductor prices coming down as far as they have I think the world has probably fundamentally changed for FPGAs and the niche they occupied is shrinking fast.
If you have central control you might even be able to get away with changing the rules. i.e. most roads are now one-way leading out of the city. voilà we nearly doubled outbound throughput. Even just for commuting that would be awesome, not that it is happening anytime soon, but one can dream, especially while sitting in gridlock traffic.
Having the middle of five lanes change direction depending on the hour is fairly common. There's even a dedicated machine to move a concrete barrier to support this.
“ Minnesota House File 1606 would allow survivors to sue the owners of nudification apps for damages “
I have no idea how the law works in this case but if you could prove damages couldn’t you already sue? This is a guess but maybe this law clarifies what is considered damaging which is what enables them to prove damages where under previous definitions they couldn’t?
I'm confused, isn't the whole point of using the STM32CubeIDE that all the peripherals, like say setting up an ADC on pins 4 and 7, are checkbox features?
> use cases related to root causing complex simulation failures.
That's a pretty interesting use case. I assume this is for RTL simulation given the thread, but how do you connect the output of the simulator to the AI?
For a small case, a colleague took a screenshot of waves in the waveform viewer and pasted it into the AI tool. It worked.
But for large cases, use tools to extract all interfaces from the waveform file and save it as a text file, or add $display statements in the Verilog itself to dump the transactions. A SOTA LLM will eat it up. You point it to the RTL, a log file with hundreds of thousands of lines, and give it a few lines to explain how it is supposed to behave. Just tell it "My simulation is hanging. Figure why." Wait 15 minutes and it will tell you why it hangs and which line to change in your code to fix it.
I've done the experiment after the fact: I had spent ~3 days to fix complicated 3 bugs. I then rolled back the code and told it "Here is the spec. Find all the bugs in this code". It found all 3 bugs in around 30 min. That's when I realized that things won't be the same anymore. (And don't get me wrong: I love debugging simulations.)
>And why not take the alternative approach of identifying the subset of people who have indeed found solid uses and spread their best practices around?
A bottom-up approach has a far better chance of finding those particularly good use cases, and if you lean on the people how found those fits, they're more persuasive than top-down edicts. They actually know what they're talking about. If the point is to leverage AI for better work outcomes, someone with your experience is far more valuable than "here's a dashboard, make the number go up," which seems to be what's going on at Amazon.
I'd bet my life savings that the person who is forced to use a tool by top-down edict is less likely to find a valuable use case than the person who is sincerely curious about said tool.
Have you tried to change your HDL to something more modern like Bluespec System Verilog or, god forbid, anything embedded into Haskell or Scala?
I read that BSV source code is about three times shorter than similar design in Verilog and also has three times smaller defect density (defects per significant line of code). So just by changing the HDL from Verilog to BSV one can have nine (9) times less defects in the design.
BSV won't help for cases you didn't think about a corner case. (I use SpinalHDL/Scala for all my hobby projects, BTW, and yes, I tend to make less mistakes.)
Also an “exploratory discussion” is not the same as a signed contract. Apple has tons of custom silicon now. There are many low risk ASICs Apple could kick the tires with.
https://www.amd.com/en/corporate/university-program.html
You can get free licenses and donated hardware through this program.
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