Also, RISC began at a time when main memory was actually slightly faster than the CPU[1], and the bottleneck for the contemporary CISCs was instruction decoding. With memory bandwidth to spare, it made a lot of sense to simplify the decoders to make them faster, resulting in sparser encodings which used more storage and bandwidth. Had memory always been slower, perhaps things would've turned out very differently - multicycle decoders and more complex instruction sets might've become far more common, and less caching.

[1] If I remember correctly, I saw the graph showing this memory-faster-than-CPU in the famous Hennessy&Patterson book, which is somewhat ironic since it quite heavily preaches about the virtues of MIPS.