"The argument is this: to an (admittedly over-simplified) approximation an ASIC and an FGPA have the same gates, it's just the interconnects that are different."
No, they don't. The FPGA's have LUTS that represent other logic gates in weird ways for flexibility. They also have traditionally, software-programmed macro-cells like DSP's and MAC's which are logic programmed. And there's an interconnect and power-saving tricks on top of that. Different enough that properly synthesizing to FPGA's is a different subfield with different techniques and sometimes 5 to 6-digit software to do it well on heterogenous tiles. I got simpler, free ones that can synthesize or optimize logic with primitive gates.
"The lower the power and space efficiency of the interconnect, the larger the incentive is to put ASIC-style interconnected gates into little islands in the FPGA fabric - hence the various complex tiles like MACs that you mention."
"At that point there's no real advantage to having those complex tiles, because the equivalent configured FPGA circuit is just as efficient, so you might as well take advantage of the flexiblity of a completely uniform fabric."
You seem to be looking at the technical aspect for the simplest and most elegant solution. Bets on that usually fail because what drives these markets is consumer demand and what's good for business. Consumer demand wants things faster, cheaper, optimized for their use case, and so on. That, not interconnects or whatever, prompted the creation of complex tiles that could accelerate their workload. SOC, HPC, and cloud server markets have been going in same direction with offload engines for same reason.
The other end of the problem are the suppliers. They know that they need to differentiate to sell more chips. So, they create chips with different specs, new types of LUTS, onboard I.P., accelerators, and so on. They, academics, and startups then create tools to try to utilize them effectively. Consumer demand for this sort of things isn't going away and neither is the need to differentiate with them. So, this pattern will remain regardless of technical arguments as it always has in every part of computing industry.
So, we get to nanoscale memory, nanowires, nano-FPGA's... whatever fictional, better tech you want. So, they get created. Now, everyone has super-fast, low-power chips with tons of logic. Parkinson's Law and the above pattern kick in: companies need to differentiate, solution providers start using exponentially more resources for their competitiveness, and users want ways to run these cheaper/faster/whatever. So, they start adding I.P., using different types of nano-blocks, getting clever with interconnects, and so on.
In other words, you've swapped out the physical components but changed nothing that drove them to complexity in the first place. The drivers will still be there in age of nano-FPGA's. So, they'll still be complex, consumers appetites will still be insatiable, and EDA runtimes will be higher than ever. This outcome is always the safe bet.
"No, they don't. The FPGA's have LUTS that represent other logic gates in weird ways for flexibility."
LUTs are composed of gates. By gates I mean literal transistors etched in the silicon. They're the simplest form of optimization that FPGAs use to get around the cost of re-routable interconnects.
However, you seem to be missing my point: that complex tiles will no longer be an advantage, for performance or for differenciation. We're reaching the bottom of what silicon can do, and the rules of the game are going to change - the future isn't going to be just smaller and faster versions of the same thing we have now.
And while I agree that differenciation is a powerful driver, it happens just as often as not that the ability to differenciate goes away. That's how we get commoditization. Certainly there will be still be the ability to differenciate based on the various analog peripherals on the chip (GPIOs, DACs, etc.), but in terms of the actual digital FPGA fabric, I think that will go away, and the benefits of standardization and reduced SKUs (i.e. in terms of supply-chain management and economies of scale) will start to win out.
And, certainly the market-driven complexity you talk about will always exist, but it will be driven from the silicon side of it.
"And, certainly the market-driven complexity you talk about will always exist, but it will be driven from the silicon side of it."
I really doubt that given what markets done so far. I hope you're right, though. It would make things so much better for us. I won't bet on it but I'd like it to happen.
No, they don't. The FPGA's have LUTS that represent other logic gates in weird ways for flexibility. They also have traditionally, software-programmed macro-cells like DSP's and MAC's which are logic programmed. And there's an interconnect and power-saving tricks on top of that. Different enough that properly synthesizing to FPGA's is a different subfield with different techniques and sometimes 5 to 6-digit software to do it well on heterogenous tiles. I got simpler, free ones that can synthesize or optimize logic with primitive gates.
"The lower the power and space efficiency of the interconnect, the larger the incentive is to put ASIC-style interconnected gates into little islands in the FPGA fabric - hence the various complex tiles like MACs that you mention."
"At that point there's no real advantage to having those complex tiles, because the equivalent configured FPGA circuit is just as efficient, so you might as well take advantage of the flexiblity of a completely uniform fabric."
You seem to be looking at the technical aspect for the simplest and most elegant solution. Bets on that usually fail because what drives these markets is consumer demand and what's good for business. Consumer demand wants things faster, cheaper, optimized for their use case, and so on. That, not interconnects or whatever, prompted the creation of complex tiles that could accelerate their workload. SOC, HPC, and cloud server markets have been going in same direction with offload engines for same reason.
The other end of the problem are the suppliers. They know that they need to differentiate to sell more chips. So, they create chips with different specs, new types of LUTS, onboard I.P., accelerators, and so on. They, academics, and startups then create tools to try to utilize them effectively. Consumer demand for this sort of things isn't going away and neither is the need to differentiate with them. So, this pattern will remain regardless of technical arguments as it always has in every part of computing industry.
So, we get to nanoscale memory, nanowires, nano-FPGA's... whatever fictional, better tech you want. So, they get created. Now, everyone has super-fast, low-power chips with tons of logic. Parkinson's Law and the above pattern kick in: companies need to differentiate, solution providers start using exponentially more resources for their competitiveness, and users want ways to run these cheaper/faster/whatever. So, they start adding I.P., using different types of nano-blocks, getting clever with interconnects, and so on.
In other words, you've swapped out the physical components but changed nothing that drove them to complexity in the first place. The drivers will still be there in age of nano-FPGA's. So, they'll still be complex, consumers appetites will still be insatiable, and EDA runtimes will be higher than ever. This outcome is always the safe bet.