SystemVerilog supports structs and unions. Synthesizable constructs are up to the synthesis tool to infer, and they are very clear as to how they work.
Any HDL language will be confusing to someone who isn't used it because you are defining a set of parallel behaviours and responses to specific stimulus and not a set of instructions.
There can always be improvements but as of today Sys/Verilog is the most popular by far, followed by VHDL. Therefore the tool vendors support those languages which is what I was responding in the original post.
Any HDL language will be confusing to someone who isn't used it because you are defining a set of parallel behaviours and responses to specific stimulus and not a set of instructions.
There can always be improvements but as of today Sys/Verilog is the most popular by far, followed by VHDL. Therefore the tool vendors support those languages which is what I was responding in the original post.