The transistor count of an A11 is 4.3 million, the Ryzen has about 4.8 million depending on the type. And x86 is a bit wasteful in terms of what it does effectively with those transistors because the front-end required to translate x86 instructions.
And x86 is a bit wasteful in terms of what it does effectively with those transistors because the front-end required to translate x86 instructions.
That's a tiny amount in comparison to all the other pieces like cache, ultrawide SIMD units, and bus interfaces; and given that it acts as a sort of "decompressor" interfacing the slower memory containing denser instructions with the faster core and its wide uops, I'd say those transistors are quite well spent.
AArch32 is about as compilcated as x86 to decode. About 1200 instructions with dozens of different encodings, and instructions that aren't aligned to instruction width and can straddle a page and cache line boundary.
This may be part of the reason why no A11-based devices support AArch32. iOS 11 dropped support for 32-bit apps, and its highly possible the chip doesn’t support the ISA at all.
