The MIT CONS computer and its commercial descendants at Symbolics and
LMI was not a parallel architecture. It was a fairly conventional
uniprocessor CPU which happened to have a register and instruction
architecture that provided some hardware acceleration for typical
"LISP" tasks (specifically tagged pointers: the "pointer" value had a
bit telling the CPU whether to load the value as-is or indirect
through it to load the next value).
As for why they were expensive: they were small market pre-VLSI
minicomputers being sold in the late 70's and early 80's. They
competed most directly with machines like the MicroVAX, and weren't
particularly expensive for that market, AFAIK. Assembling and testing
a few thousand ICs into a single computer is just inherently
expensive.
As for why they were expensive: they were small market pre-VLSI minicomputers being sold in the late 70's and early 80's. They competed most directly with machines like the MicroVAX, and weren't particularly expensive for that market, AFAIK. Assembling and testing a few thousand ICs into a single computer is just inherently expensive.