>The main task for any BIOS is to initialize the memory controller, which for modern DDR4 or DDR5 memory is a very complex and undocumented task, so it must be done usually by a binary firmware blob provided by Intel or AMD.
I don't question that binary blobs are distributed by Intel or AMD...
I also don't question that DDR5 memory is probably more complex (since it is newer, and newer technology is usually more complex) than DDR4, which is probably more complex than DDR3, etc., etc.
But, on a purely conceptual level, RAM is not all that complex... It's ridiculously simple. On a conceptual level, RAM is just a bunch of wires where most of those wires determine the address, some of those wires are for power, clock signal and ground, and some other of those wires move data back and forth to the CPU. Not complex at all!
The memory needs to be initialized? Well, maybe on startup it needs to be quickly calibrated/tested to make sure that a given RAM will work at a given frequency, but again, not rocket science!
If a memory controller requires a lot of complex initialization -- then maybe it isn't designed right?
A well-designed memory controller (if it were well designed) -- should abstract away details of what it does with the underlying memory such that it presents a single, simple, easy-to-understand, easy-to-initialize, unified, homogenous interface to memory.
In other words, no need for a lot of BIOS initialization code or black box binary blobs -- IF it is created correctly...
Somone doesn't like Intel or AMD black box binary blobs?
Well, people have (and I'm guessing more will, over time!) implemented their own memory controllers running on FPGA's...
But I'll let the statement "DDR5 memory is a very complex and undocumented task, so it must be done usually by a binary firmware blob provided by Intel or AMD." stand for now.
I don't question that binary blobs are distributed by Intel or AMD...
I also don't question that DDR5 memory is probably more complex (since it is newer, and newer technology is usually more complex) than DDR4, which is probably more complex than DDR3, etc., etc.
But, on a purely conceptual level, RAM is not all that complex... It's ridiculously simple. On a conceptual level, RAM is just a bunch of wires where most of those wires determine the address, some of those wires are for power, clock signal and ground, and some other of those wires move data back and forth to the CPU. Not complex at all!
The memory needs to be initialized? Well, maybe on startup it needs to be quickly calibrated/tested to make sure that a given RAM will work at a given frequency, but again, not rocket science!
If a memory controller requires a lot of complex initialization -- then maybe it isn't designed right?
A well-designed memory controller (if it were well designed) -- should abstract away details of what it does with the underlying memory such that it presents a single, simple, easy-to-understand, easy-to-initialize, unified, homogenous interface to memory.
In other words, no need for a lot of BIOS initialization code or black box binary blobs -- IF it is created correctly...
Somone doesn't like Intel or AMD black box binary blobs?
Well, people have (and I'm guessing more will, over time!) implemented their own memory controllers running on FPGA's...
Some of them are up to DDR4 capabilities...
https://github.com/oprecomp/DDR4_controller
https://www.google.com/search?q=open+source+ddr4+ip+core
But I'll let the statement "DDR5 memory is a very complex and undocumented task, so it must be done usually by a binary firmware blob provided by Intel or AMD." stand for now.
Yes, that's true as of 2022...
But will that continue to remain true?
?