As someone in the risc-v education space, it has been very cool to see RIPES develop. It seems like I blinked and it gained a lot of features. It gives you the most information about how a program might run.
If you would rather focus on the software and you want to try learning risc-v assembly, I would recommend the simulator I made https://github.com/TheThirdOne/rars .
This is the tool I needed while taking the computer architecture series in college. An animated simulation would have gotten me up to speed much faster. Working through each instruction using a pencil and paper was a slow process that would have been more beneficial after seeing a simulation run a few times.
Might one do a cache-aware code competition? Given the simulator's determinism and cache.
As attention to cache-friendly data layout seems often lagging its importance ... err, and the world doesn't yet have enough premature optimization.
Implement this algorithm; it will be challenged with <large n> input sets; here is a training set generator; your competition set runtimes will be aggregated with <metric>; minimize it.
Cache-oblivious code is a lot more successful in the real world, because systems change over time. Hardwiring code to rely on a rigidly predefined amount of cache is the worst kind of premature optimization.
Isn’t “a lot more successful” is only true more generally? Many developers have fixed platform targets for the life of a product (e.g., consoles, embedded, microarch). So I’d agree in general but hesitate to say “a lot more successful”.
So the concern is overfitting to a single target? Hmm, then perhaps: here are several/parameterized cache models to develop on; one/several will be used to judge the competition?
> Cache-oblivious code is a lot more successful [...] Hardwiring code to rely on a rigidly predefined amount of cache is the worst
Yes, but ... Creating cache-oblivious code requires devs non-oblivious to cache. Perhaps a kata/competition might encourage such.
Accessing cachelab.tar there regrettably requires login. Also on https://csapp.cs.cmu.edu/public/labs.html . Though the other Cache Lab links work. But googling "cachelab" currently turns up similar elsewhere. And a few students' solutions. Tnx!
This is super cool! I have not had time yet to play with it properly but just running some sample code and watching the animated stepping is insanely nice and very educational! Thanks.
If you would rather focus on the software and you want to try learning risc-v assembly, I would recommend the simulator I made https://github.com/TheThirdOne/rars .