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I probably shouldn't have said "new" without explaining myself more.

For safety- and mission-critical applications (SC and MC), Verilog is more established in the US, and VHDL is more established in Europe.

For SC, a tool doesn't get any points unless you've used it yourself, so the fact that they occupy the same role and have similar pedigree elsewhere is nearly irrelevant. Each tool permeates all the way down to the less critical roles in order to establish it for more critical use by those specific companies and government agencies. That's how these tools get entrenched in different places.

For MC, you can bring things into your company or agency that are relatively new to your organization or less used in your organization. This processor would at most be used for MC and it's a significant new capability, so it's not all that weird.



That argument essentially boils down to "they wanted to try it", but I don't think that it explains why they would want to try it. Verilog is arguably worse from a verification standpoint, which is afaik the main reason why VHDL won out in Europe. Pretty much every academic hardware working group that I encountered is also a formal verification working group.


That's not the argument I thought I was making.

The lower the application criticality and the bigger the project impact, the more leeway you can give if there are legitimate project-killing limitations. It's safe to say that the project is impactful because it adds an important sovereign capability, and low criticality because it won't be used for safety and it's not already slated for use in a flagship mission as a mission-killing component.

The only assumption you have to make is why VHDL would be bad. Could be a technical limitation that would be prohibitively expensive to fix. Could be that this group is coming from a non-space background in Verilog and switching to VHDL would be too long and expensive. Or maybe it's a long-term strategic decision to advance the use of Verilog in space because the ESA feels like VHDL will become a liability in the future.




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