It took me to the end of your comment to realise the crucial bit I was missing: ...

		cjbillington 12 months ago \| parent \| context \| favorite \| on: A FPGA friendly 32 bit RISC-V CPU implementation It took me to the end of your comment to realise the crucial bit I was missing: that they're talking about implementing the CPU on an FPGA. As opposed to, say, interfacing with an FPGA which could be totally different way to be "FPGA-friendly".