Technically it's running software on the programmable I/O, but that software is just a loop of four outputs that advances when it gets a 1 bit and doesn't advance when it gets a 0 bit. It feels like the hardware that manages the buffer and turns it into a high speed serial stream is doing the more important work here.

And the CPU that's actually deciding on the bits doesn't have to bang them with precise timing, it just has to put them into that buffer.

Yeah but like FPGA fabric can also be programmed (sometimes by actual software like on Zynq or Stratix SoCs), would you call those bit banging too?

I feel most people would unless you use some Hard IP for the interface. Like you don't bit-bang PCIe when you feed a wide AXI stream at a few MHz into the PCIe block where it get's serialized and put onto the lanes at the signalling rate (multiple Gigahertz, depending on generation).

I don't have any hands-on experience with FPGAs. I only know about as much about FPGAs as I do about red herring.