What pattern in the data shows that's what's being measured? I would expect to s... | Hacker News

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		Neywiny 17 days ago \| parent \| context \| favorite \| on: Nvidia GB10's Memory Subsystem, from the CPU Side What pattern in the data shows that's what's being measured? I would expect to see basically 0 latency between adjacent "cores" then since L1 is shared per thread?

monocasa 17 days ago [–]

Co resident threads might not get any speed up here since coherency instructions are functionally operations on the L2 cache.

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