This... Actually might be the first AI product I'd ask my work to look into. I've had only one schematic reviewer out of the group catch that a part I'd re-used elsewhere in a design I inherited to reduce complexity + increase configurability actually didn't meet the voltage I needed for it. That example at the start is exactly what was needed and how it was found+fixed. Check the datasheets, check the schematic.

Only concern is the datasheet limit. We tend to have bigger designs than that. Also we're not using KiCAD but maybe it could export.

So glad to hear that! Regarding the datasheet limit: the current Pro plan caps projects at 40 datasheets, but this is not a hard technical limit. For enterprise customers, we can raise this cap. The primary constraint is inference cost — once you go beyond ~40 datasheets, meaningful cross-checking can consume Pro-plan usage very quickly. For teams that are less cost-sensitive, a higher-tier plan with increased limits is feasible.

On EDA tool support, we can work with any tool that exports a netlist. If you can export to .EDIF, it should work out of the box, as this is the format we accept for Altium designs. The schematic visualizer currently supports KiCad only, but we are exploring how to parse full project files from other tools to provide the same visualization and extract additional metadata.

If your team has a formal procurement process, feel free to reach out via the contact email on our site.

I may mention it for my next schematic, but they'd probably want to understand the data flow and run everything locally. In that this is a wrapper around the other models (and full credit due, clearly not just a dumb wrapper like an extra prompt at the front of a chat bot), this should be possible, yes? Run the part that queries the models locally, point that to our locally hosted LLMs, and we're good?

Otherwise we probably couldn't put many designs of substance in. Just the data security risk.

I may reach out from my corporate email tomorrow. It's public who I am and where I work but yes we certainly have a formal procurement process.

Cool! Earlier in 2025 I decided I wanted to design a CAN-FD connected motor controller for RRF / Klipper / custom firmware without any experience.

I'm a software eng now working outside of the tech sphere so not exactly an electronics expert. I know enough to be dangerous but thats about it.

I found Gemini to be pretty great at validating an exported KiCAD netlist against the relevant datasheets with a few caveats.

The RP2350 datasheet in particular was an issue due to its sheer size - bigger than the maximum token limit.

I got around this by extracting the relevant parts of the datasheet myself.

It sounds like you might have this well in hand but worth asking anyway. I assume you've had good experiences testing with MCU datasheets and not just passives / power components?

When it got something wrong it was wrong enough to be noticeable by a non expert and with iterations over the schematic and an incredible amount of time spent learning how to lay stuff out properly, I got a reasonably complex board (double sided, 6 layer, roughly 130 components) produced and fully functional first time.

I'm interested in trying this out on my working design and seeing what it comes up with!

If you can keep this cheap enough for hobby use (or pay as you go for example) and also find a way to validate or check for common layout concerns then that would be incredibly powerful.

It's great to see some genuinely useful use cases for LLM tech that isn't just "we replaced our support people with a shitty chat bot" :)

I don’t see how you would get a good training set on this or put it in a format that LLMs understand

I was puzzled a bit, then realized they only handle schematics. Saying "PCB schematics" is weird.

A schematic is just a representation of a netlist, something where text is more than fine since the graphical form is only for human consumption. An LLM is actually a pretty good fit to cross-reference datasheets and netlists.

Would it be actual PCB layout I would be skeptical as LLMs are quite poor at anything spatial. For schematics however, it could work quite well as a double check.

I don’t buy that it would be very good at reliably finding problems in schematics either. There’s no big dataset on the internet to train on

Some anecdata: This weekend as a lark I asked Claude Code to design a (fairly simple) analog circuit and simulate it in LTSpice to verify. It did three edit-simulate-fix cycles and to my surprise ended up with something that seemed pretty sane.

That said, schematics (as opposed to netlists) don't seem to be a practical I/O format yet. It did generate a KiCad schematic file when asked, but it was pretty bad (penguin on a bicycle level).

Anyway, somehow there does seem to be some electronic tools training happening, becuase I tried this maybe a year ago and it was pretty hopeless.

This is exactly why the first version of our tool worked with netlists only. We've since evolved to parsing the full KiCad project and generating a netlist from it so we can also extract schematic-specific metadata that doesn't make it into the netlist (designer notes/annotations, component positions, etc.)

This looks great, but I want to know when LLMs will be useful for generating schematics rather than just checking them! It’s such a letdown right now to jump from doing firmware with Claude Code to drawing schematics manually like it’s 2022. :) When does KiCad get its little assistant pane on the right?

Schematic generation doesn’t really make sense to me because the cost of a problem going unnoticed is much more significant in hardware design than software.

cool, how did you connect claude to ltspice?

I just told Claude Code to use the command line LTSpice tool. Actually, I'm not even sure I did that much, I may have just told it to "use LTSpice"!

Ive had that argument with many of the schematic PCB ai startups. Online open source schematics and PCB designs are awful training sets by large. There are some gems out there publicly but that's gems in a sea of sand. Far different than training a LLM on all the published books of the world.

Not sure how familiar you are with KiCad but its project files are just text. With a little bit of rearranging you can get things like:

"Component U1 is 74HCT02, has 14 pins"

"Component R2 is 4.7K resistor, has 2 pins"

"Signal +5V connects U1 pin 14, U2 pin 9, R1 pin 2, R7 pin 1...."

"Signal /RESET connects U1 pin 2, U4 pin 3, U7 pin 8...."

If you get this dialed in, you could charge a LOT more. Your big market is enterprise customers that need to review schematics that are 30 pages long with FPGAs, memory busses, and lots of connectors. You should segment the hobbyist for the $10-20/month and then enterprise customers at $+100/month. If your product catches just one major problem in a schematic, it could save a full revision which is worth thousands of dollars.

Fantastic idea. I've done some PCB stuff in the distant past. But not recently.

I wish I had some examples to test against this.

Best of luck going forward. This is the kind of tool that could make a difference.

Previously:

Show HN: An LLM-Powered Tool to Catch PCB Schematic Mistakes - https://news.ycombinator.com/item?id=46080737 - Nov 2025 (29 comments)

Looks pretty neat, but you really need to have Cadence (OrCAD or System Capture) format support to scale to larger organizations. Most larger hardware companies aren't using KiCAD or Altium outside of one-off projects.

Thanks for the feedback -- we’re actively looking into this and will keep the HN community updated as we roll out support for more enterprise-focused tools

Can it detect problems in basic schematics consisting of say 5-10 transistors, and perhaps a bunch of resistors and capacitors?

Would it be able to detect issues with functionality, and maximum ratings?

Yes. I’d recommend trying the free plan with your design to see how it performs. You can also steer the review in a specific direction using custom instructions in "Advanced Options" if there are particular parts of the design you want analyzed.