Ah the pentium, aka 5-ium due to the penta- prefix. It is actually a nod from 4 to 5, but Intel wanted some cool name, and they decided penta + premium would sound cool, hence pentium.
But still, internally we call it i586, because that's the way it is. so is Pentium MMX which I reckon is called i686.
Yes, and Intel had actually lost a legal attempt to stop people using the numbers (I can't remember if this was earlier in the 486 era or if it was something they tried first with 586).
But marketing was a large part of the reason that they started caring so much at that particular time. The Pentium line was the first time Intel had marketed directly to the end users¹² in part as a response to alt-486 manufacturers (AMD, Cyryx) doing the same with their products⁴ like clock-doubled units compatible with standard 486/487 targetted sockets (which were cheaper and, depending on workload, faster than the Intel upgrade options).
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[1] this was the era that “Intel Inside (di dum di dum)” initially came from
[2] that was also why the FDIV bug was such a big thing despite processor bugs³ being, within the industry, an accepted part of the complex design and manufacturing process
[3] for a few earlier examples: a 486 FPU bug that resulted in what should have been errors (such as overflow) being silently ignored, another (more serious) one in trig functions that resulted in a partial recall and the rest of that line being marked down as 486SX units (with a pin removed to effectively disable the FPU), similarly an entire stepping of 386 chips ended up sold as “for 16 bit code only”, going further back into the 8-bit days some versions of the 6502 had a bug or two in handling things (jump instructions, loading via relative references) that straddled page boundaries (which were mitigated in code by being careful with code/data alignment, no recalls, just errata published)
I remember when IBM was upset that various companies were calling their 80286 computers "<Brandname> AT" like the IBM AT ("advanced technology"). But you can't trademark a preposition!
If I am correct, the Pentium Pro was the first "out of order" design. It specialized in 32-bit code, and did not handle 16-bit code very well.
The original Pentium I believe introduced a second pipeline that required a compiler to optimize for it to achieve maximum performance.
AMD actually made successful CPUs based on Berkeley RISC, similar to SPARC (they used register windows). The AMD K5 had this RISC CPU at its core. AMD bought NexGen and improved their RISC design for the K6 then Athlon.
Because of the branding change, history will remember the Pentium (P5). It was really the Pentium
Pro (P6) that put Intel leaps ahead on x86 microarchitecture, a lead they’d hold with only a few minor stumbles for two decades.
Bob Colwell (mentioned elsewhere ITT) wrote a fascinating technical history of the P6: The Pentium Chronicles.
The major stumble being having to cross licence AMD for the x64 opcode design thus ensuring at least two players in the field (and due to how it's going only two).
They also started to slip behind AMD in the Pentium 4/NetBurst era, but got their footing back with Core (a more direct descendant of the P6 than the Pentium 4!)
Around the same time, but I’d classify as separate stumbles.
I'm really not sure if POWER1 and PowerPC 603 should be counted as OoO or not.
It's certainly not the same kind of OoO. They had register renaming¹, But only enough storage for a few renamed registers. And they didn't have any kind of scheduler.
The lack of a scheduler meant execution units still executed all instructions in program order. The only way you could get out-of-order execution is when instructions went down different pipelines. A floating point instruction could finish execution before a previous integer instruction even started, but you could never execute two floating point instructions Out-of-Order. Or two memory instructions, or two integer instructions.
While the Pentium Pro had a full scheduler. Any instruction within the 40 μop reorder buffer could theoretically execute in any order, depending on when their dependencies were available.
Even on the later PowerPCs (like the 604) that could reorder instructions within an execution unit, the scheduling was still very limited. There was only a two entry reservation station in front of each execution unit, and it would pick whichever one was ready (and oldest). One entry could hold a blocked instruction for quite a while many later instructions passed it through the second entry.
And this two-entry reservation station scheme didn't even seem to work. The laster PowerPC 750 (aka G3) and 7400 (aka G4) went back to singe entry reservation stations on every execution unit except for the load-store units (which stuck with two entries).
It's not until the PowerPC 970 (aka G5) that we see a PowerPC design with substantial reordering capabilities.
¹ well on the PowerPC 603, only the FPU had register naming, but the POWER1 and all later PowerPCs had integer register renaming
Interesting, apparently it did scoreboarding like the CDC6600 and allowed multiple memory loads in flight, but I can't find a definite statement on whether it did renaming (I.e. writes to the same registers stalled). It might not be OoO as per modern definition, but is also not a fully on-order design.
> The original Pentium I believe introduced a second pipeline that required a compiler to optimize for it to achieve maximum performance.
It wasn't a full pipeline, but large parts of the integer ALU and related circuitry were duplicated so that complex (time-consuming) instructions like multiply could directly follow each other without causing a pipeline bubble. Things were still essentially executed entirely in-order but the second MUL (or similar) could start before the first was complete, if it didn't depend upon the result of the first, and the Pentium line had a deeper pipeline than previous Intel chips to take most advantage of this.
The compiler optimisations, and similar manual code changes with the compiler wasn't bright enough, were to reduce the occurrence of instructions depending on the results of the instructions before, which would make the pipeline bubble come back as the subsequent instructions couldn't be started until the current one was complete. This was also a time when branch prediction became a major concern, and further compiler optimisations (and manual coding tricks) were used to help here too, because aborting a deep pipeline because of a branch (or just stalling the pipeline at the conditional branch point until the decision is made) causes quite a performance cost.
The Pentium was not just pipelined but also superscalar; it had two pipelines (U and V). U implemented all instructions, V only implemented a subset of simpler ones, and only when using simple (prefix-less) encodings.
As the CPU was not out of order, to execute two instructions per clock you had to pair them so that the second one was simple, and did not use the output of the first one. Existing code and most compilers around at the time were generally bad at this, but things like inner render loops in games could make a lot of use if you wrote them in assembly.
Por qué no los dos? If "-ium" makes nerds think of an element name, and others of a premium product, all the better. I'd bet both of these interpretations were listed in the original internal marketing presentation of the name...
> but Intel wanted some cool name, and they decided penta + premium would sound cool, hence pentium
some say that they tried to add 486 with 100 and the result had some numbers after the comma, that's why they named it pentium (yes, i know about the FDIV bug)
But still, internally we call it i586, because that's the way it is. so is Pentium MMX which I reckon is called i686.