It was my impression that SPARC, as an instruction set architecture, has been somewhat discredited.

While not an instruction-set feature, I find the register windows thing very interesting.

Interesting and wrong-headed: the idea was both to optimize the architecture for C functional calls and to allow the processor to "scale" (hence the name) by adding to the register file without breaking the ABI (which you'd have to do to, say, add an %EFX register to x86).

But: call stack depth on modern programs pushed register performance up against L1 cache performance for the C stack, and SPARC's convolution register spill/fill seems to have been a liability. More importantly, adding registers has not over the last decade been the primary mechanism by which processor speed is "scaled".

There are hardware people here that could articulate this more accurately and correctly than me; I've got some SPARC assembly game, but I'm not a hardware design guy. But when I say the ISA has been discredited, I'm talking about things like register windows.

I would love to hear from the hardware guys why SPARC ISA is such a bad idea.

Here's a decent comp.arch post making the same point (more precisely and accurately than me, but still pretty casually):

http://yarchive.net/comp/register_windows.html